thesis compact model

Mathematical Compact Models of Advanced Transistors for Numerical Simulation and Hardware Design

Juan duarte, eecs department, university of california, berkeley, technical report no. ucb/eecs-2018-24, may 2, 2018, http://www2.eecs.berkeley.edu/pubs/techrpts/2018/eecs-2018-24.pdf.

Mathematical compact models play a key role in designing integrated circuits. They serve as a medium of information exchange between foundries and designers. A compact model, which is a set of long mathematical equations based on the physics of each transistor, is capable of reproducing the very complex transistor characteristics in an accurately, fast, and robust manner. This dissertation presents the latest research on compact models for advanced transistor technologies: FinFETs, Ultra-thin body SOIs (UTBSOIs), Gate-All-Around (GAA) FETs, and Negative Capacitance (NC) FETs.

Since traditional transistor scaling had reached limitations due short-channel effects and oxide tunneling, the introduction of FinFET and UTBSOIs in high-volume manufacturing at 20nm, 14nm and 10nm technology nodes had let the electronic industry to keep obtaining performance and density advantages in technology scaling. For smaller nodes such as 5nm, and 3nm, GAA FETs transistors are expected to replace traditional transistors. Production ready compact model for current and future FinFETs are presented in this thesis. The Unified Compact Model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. A new quantum effects model will also be presented, it enables accurate modeling of III-V FinFETs. Shape agnostic short-channel effect model for aggressive LG scaling and body bias model for FinFETs on bulk substrates are also included in this work. This computationally efficient model is an ideal turn-key solution for simulation and design of future heterogeneous circuits.

For extremely scaled technologies, NC-FETs are quickly emerging as preferred candidates for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has led to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.

This thesis gives insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in commercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping to minimize the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, VDD scaling becomes more dominant on energy reduction of NC-FinFET based circuits.

Advisors: Chenming Hu

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Compact Modeling

Principles, Techniques and Applications

• © 2010
• Gennady Gildenblat 0

, Sch Elect Comptr & Energy Engr, Arizona State University, Tempe, USA

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• A comprehensive book on compact models of most commonly used semiconductor devices
• Each chapter is covered by an expert, often responsible for the widely used model with wide industrial applications
• Both traditional and experimental devices are covered
• Critical variability issues are addressed
• Provides detailed coverage of compact model benchmarking which is critical for model development and applications
• Includes supplementary material: sn.pub/extras

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Table of contents (16 chapters)

Front matter, compact models of mos transistors, surface-potential-based compact model of bulk mosfet.

• Gennady Gildenblat, Weimin Wu, Xin Li, Ronald van Langevelde, Andries J. Scholten, Geert D. J. Smit et al.

PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs

• Weimin Wu, Wei Yao, Gennady Gildenblat

Benchmark Tests for MOSFET Compact Models

• Xin Li, Weimin Wu, Gennady Gildenblat, Colin C. McAndrew, Andries J. Scholten

High-Voltage MOSFET Modeling

• E. Seebacher, K. Molnar, W. Posch, B. Senapati, A. Steinmair, W. Pflanzl

Physics of Noise Performance of Nanoscale Bulk MOS Transistors

• R. P. Jindal

Compact Models of Bipolar Junction Transistors

Introduction to bipolar transistor modeling.

• Colin C. McAndrew, Marcel Tutt
• R. van der Toorn, J. C. J. Paasschens, W. J. Kloosterman, H. C. de Graaff

The HiCuM Bipolar Transistor Model

• Michael Schröter, Bertrand Ardouin

Compact Models of Passive Devices

Integrated resistor modeling.

• Colin C. McAndrew

The JUNCAP2 Model for Junction Diodes

• A. J. Scholten, G. D. J. Smit, R. van Langevelde, D. B. M. Klaassen

Surface-Potential-Based MOS Varactor Model

• Zeqin Zhu, Gennady Gildenblat, James Victory, Colin C. McAndrew

Modeling of On-chip RF Passive Components

Modeling of multiple gate mosfets, multi-gate mosfet compact model bsim-mg.

• Darsen Lu, Chung-Hsun Lin, Ali Niknejad, Chenming Hu

Compact Modeling of Double-Gate and Nanowire MOSFETs

Statistical modeling.

• Compact models
• Leistungsfeldeffekttransistor
• Variability
• bipolar junction transistor
• bipolar power transistor
• field-effect transistor
• integrated circuit
• metal oxide semiconductur field-effect transistor
• semiconductor

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Editors and Affiliations

, sch elect comptr & energy engr, arizona state university, tempe, usa.

Gennady Gildenblat

Bibliographic Information

Book Title : Compact Modeling

Book Subtitle : Principles, Techniques and Applications

Editors : Gennady Gildenblat

DOI : https://doi.org/10.1007/978-90-481-8614-3

Publisher : Springer Dordrecht

eBook Packages : Engineering , Engineering (R0)

Copyright Information : Springer Science+Business Media B.V. 2010

Hardcover ISBN : 978-90-481-8613-6 Published: 08 September 2010

Softcover ISBN : 978-94-007-9324-8 Published: 30 September 2014

eBook ISBN : 978-90-481-8614-3 Published: 22 June 2010

Edition Number : 1

Number of Pages : XVII, 527

Topics : Circuits and Systems

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• Preface. Part I. Compact Models of MOS Transistors.
• 1. Surface-Ppotential-Based Compact Model of Bulk MOSFET.
• 2. PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs.
• 3. Benchmark Tests for MOSFET Compact Models .
• 4. High-Voltage MOSFET Modeling.
• 5. Physics of Noise Performance of Nanoscale Bulk MOS Transistors. Part II Compact Models of Bipolar Junction Transistors.
• 6. Introduction to Bipolar Transistor Modeling.
• 7. Mextram.
• 8. The HiCuM Bipolar Transistor Model. Part III. Compact Models of Passive Devices.
• 9. Integrated Resistor Modeling.
• 10. The JUNCAP2 Model for Junction Diodes.
• 11. Surface-Potential-Based MOS Varactor Model.
• 12. Modeling of On-chip RF Passive Components. Part IV. Modeling of Multiple Gate MOSFETs.
• 13. Multi-Gate MOSFET Compact Model BSIM-MG.
• 14. Compact Modeling of Double-Gate and Nanowire MOSFETs. Part V. Statistical Modeling.
• 15. Modeling of MOS Matching.
• 16. Statistical Modeling Using Backward Propagation of Variance (BPV). Index.
• (source: Nielsen Book Data)

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Computer Science > Emerging Technologies

Title: compact device models for finfet and beyond.

Abstract: Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

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Basics of Compact Model Development

By Sivakumar P Mudanai

Intel Corporation, Santa Clara, CA

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This tutorial is aimed at developing an understanding of what a compact model is, the need and role of compact models in the semiconductor industry and the requirements that a compact model must meet for acceptable use in circuit simulations. The tutorial will use simple examples from planar MOSFET compact models for illustration.

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NEEDS; Nano-Engineered Electronic Device Simulation Node

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Researchers should cite this work as follows:

Sivakumar P Mudanai (2014), "Basics of Compact Model Development," https://nanohub.org/resources/21367.

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12:00 am, 10 Jun 2014

University of California Berkeley, Berkeley, CA

• Circuit Simulation
• Compact Model
• nanotransistors
• NCN Transistor @ 75
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A Physics-Based Dynamic Compact Model of Ferroelectric Tunnel Junctions

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Thermal Management Implications Of Utility Scale Battery Energy Storage Systems

The need for reducing reliance on fossil fuels to meet ever-increasing energy demands and minimizing global climate change due to greenhouse gas emissions has led to an increase in investments in Variable Energy Resources (VREs), such as wind and solar. But due to the unreliable nature of VREs, an energy storage system must be coupled with it which drives up the investment cost.

Lithium-ion batteries are compact, modular, and have high cyclic efficiency, making them an ideal choice for energy storage systems. However, they are susceptible to capacity loss over the years, limiting the total life of the batteries to 15-18 years only, after which they must be safely discarded or recycled. Hence, designing a Battery Energy Storage System (BESS) should consider all aspects, such as battery life, investment cost, energy efficiency, etc.

Most of the available studies on cost and lifetime of BESS either consider a steady degradation rate over years, or do not account for it at all, they take constant charge/discharge cycles, and sometimes do not consider ambient temperature too. This may result in an error in estimation of the cost of energy storage. The location where the BESS is supposed to be installed can also impact its life, given that each location has its own power consumption trend and temperature profile. In this work, we attempt to simulate a BESS by considering the ambient temperature, degradation rate and energy usage. This will help in getting an insight of a more realistic estimate of levelized cost of storage and for estimating the thermal energy needed to keep them within a certain temperature range, so that they can last longer.

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